Power transistor devices are often used to transport large currents and support high voltages. One example of a power transistor device is the power metal-oxide-semiconductor field-effect transistor (MOSFET). A power MOSFET has a vertical structure, wherein a source contact and a gate contact are located on a first surface of the MOSFET device that is separated from a drain contact by a drift layer formed on a substrate. Vertical MOSFETs are sometimes referred to as vertical diffused MOSFETs (VDMOS) or double-diffused MOSFETs (DMOSFETs). Due to their vertical structure, the voltage rating of a power MOSFET is a function of the doping level and thickness of the drift layer. Accordingly, high voltage power MOSFETs may be achieved with a relatively small footprint.
FIG. 1 shows a conventional power MOSFET device 10. The conventional power MOSFET device 10 includes an N-doped substrate 12, an N-doped drift layer 14 formed over the substrate 12, one or more junction implants 16 in the surface of the drift layer 14 opposite the substrate 12, and an N-doped junction gate field-effect transistor (JFET) region 18 between each one of the junction implants 16. Each one of the junction implants 16 is formed by an ion implantation process, and includes a P-doped deep well region 20, a P-doped base region 22, and an N-doped source region 24. Each deep well region 20 extends from a corner of the drift layer 14 opposite the substrate 12 downwards towards the substrate 12 and inwards towards the center of the drift layer 14. The deep well region 20 may be formed uniformly or include one or more protruding regions. Each base region 22 is formed in a shallow portion on the surface of the drift layer 14 opposite the substrate 12 within the boundaries of the deep well region 20. Each source region 24 is formed adjacent to the base region 22 in a shallow portion on the surface of the drift layer 14 opposite the substrate 12 within the boundaries of the deep well region 20. The JFET region 18 defines a channel width between each one of the junction implants 16.
A gate oxide layer 26 is positioned on the surface of the drift layer 14 opposite the substrate 12, and extends laterally between a portion of the surface of each source region 24, such that the gate oxide layer 26 partially overlaps and runs between the surface of each source region 24 in the junction implants 16. A gate contact 28 is positioned on top of the gate oxide layer 26. Two source contacts 30 are each positioned on the surface of the drift layer 14 opposite the substrate 12 such that each one of the source contacts 30 partially overlaps both the source region 24 and the deep well region 20 of one of the junction implants 16, respectively, and does not contact the gate oxide layer 26 or the gate contact 28. A drain contact 32 is located on the surface of the substrate 12 opposite the drift layer 14.
In operation, when a biasing voltage below the threshold voltage of the device is applied to the gate contact 28, and the P-N junction formed between each deep well region 20 and the drift layer 14 is reverse biased, the conventional power MOSFET device 10 is placed in an OFF state. In the OFF state of the conventional power MOSFET device 10, any voltage between the source and the drain contact is supported by the drift layer 14. Due to the vertical structure of the conventional power MOSFET device 10, large voltages may be placed between the source contacts 30 and the drain contact 32 without damaging the device.
FIG. 2 shows a three-dimensional representation of the conventional power MOSFET device 10 shown in FIG. 1. As shown in FIG. 2, the conventional power MOSFET device 10 is rectangular, essentially extending the two-dimensional representation shown in FIG. 1 into the page. As will be appreciated by those of ordinary skill in the art, the conventional power MOSFET device 10 may be tiled into or out of the page to form a conventional power MOSFET “stripe” including a plurality of conventional power MOSFET devices 10 connected in series. Further, additional power MOSFET devices may be laterally tiled with the conventional power MOSFET device 10, as shown in FIG. 3. FIG. 3 shows three conventional power MOSFET devices 10, each integrated directly adjacent to one another and connected in series. As will be appreciated by those of ordinary skill in the art, each one of the conventional power MOSFET devices 10 may be tiled into or out of the page to form a plurality of conventional power MOSFET “stripes.” Arranging the conventional power MOSFET devices 10 in “stripes” allows a large number of conventional power MOSFET devices 10 to be integrated into a small area of semiconductor die, thereby saving space in a device in which the conventional power MOSFET devices 10 are integrated.
FIG. 4A shows operation of the conventional power MOSFET device 10 when the device is in an ON state (first quadrant) of operation. When a positive voltage is applied to the drain contact 32 relative to the source contacts 30 and the gate voltage increases over the threshold voltage of the device, an inversion layer channel 34 is formed at the surface of the drift layer 14 underneath the gate contact 28, thereby placing the conventional power MOSFET device 10 in an ON state of operation. In the ON state of operation of the conventional power MOSFET device 10, current (shown by the shaded region in FIG. 4) is allowed to flow from the drain contact 32 to the source contacts 30 of the device. An electric field presented by junctions formed between the deep well region 20, the base region 22, and the drift layer 14 constricts current flow in the JFET region 18 into a JFET channel 36. At a certain spreading distance from the inversion layer channel 34 when the electric field presented by the junction implants 16 is diminished, the flow of current is distributed laterally, or spread out in the drift layer 14.
FIG. 4B shows operation of the conventional power MOSFET device 10 when the device is operating in the third quadrant. When a voltage below the threshold voltage of the device is applied to the gate contact 28 of the conventional power MOSFET device 10 and a positive voltage is applied to the source contacts 30 relative to the drain contact 32 of the device, current will flow from the source contacts through each respective base region 22 and deep well region 20 and into the drift layer 14.
As current flows from the deep well region 20 into the drift layer 14 of the conventional power MOSFET device 10 while the device is operating in the third quadrant, stacking faults may occur. Stacking faults occur as a result of basal plane dislocations (BPDs) present in the drift layer 14 due to imperfections in the semiconductor materials and/or manufacturing defects. As current runs through one or more BPDs in the drift layer 14, the crystalline structure of the semiconductor material may be altered, thereby creating one or more stacking faults. The stacking faults may substantially degrade the performance of the conventional power MOSFET device 10. For example, the stacking faults may cause the resistance of one or more areas in the drift layer 14 of the conventional power MOSFET device 10 to increase substantially.
One possible way to prevent stacking faults in the conventional power MOSFET device 10 is with more stringent manufacturing or testing of each conventional power MOSFET device 10 to reduce or eliminate BPDs. However, such manufacturing or testing procedures are often impractical or impossible, due to cost or difficulty.
An additional way to prevent stacking faults in the conventional power MOSFET device 10 is by placing an external bypass diode between the source contacts 30 and the drain contact 32 of the conventional power MOSFET device 10. FIG. 5 shows the conventional power MOSFET device 10 connected to an external bypass diode 40. As will be appreciated by those of ordinary skill in the art, the external bypass diode 40 may be chosen to be a Schottky diode, because of the low barrier voltage afforded by such a device. The external bypass diode 40 includes an anode 42, a cathode 44, and a drift layer 46. The anode 42 of the external bypass diode 40 is coupled to the source contacts 30 of the conventional power MOSFET device 10. The cathode 44 of the external bypass diode 40 is coupled to the drain contact 32 of the conventional power MOSFET device 10. The anode 42 and the cathode 44 are separated from one another by the drift layer 46.
When a bias voltage below the threshold voltage of the conventional power MOSFET device 10 is applied to the gate contact 28 of the device, and the junction between each deep well region 20 and the drift layer 14 is reverse biased, the conventional power MOSFET device 10 is placed in an OFF state and the external bypass diode 40 is placed in a reverse bias mode of operation. In the reverse bias mode of operation of the external bypass diode 40, current does not flow through the device.
FIG. 6A shows operation of the conventional power MOSFET device 10 including the external bypass diode 40 when the conventional power MOSFET device 10 is operating in on ON state (first quadrant) of operation. When a positive voltage is applied to the drain contact 32 relative to the source contacts 30 and the gate voltage increases over the threshold voltage of the device, the conventional power MOSFET is placed in an ON state (first quadrant) of operation, and the external bypass diode 40 is placed in a reverse bias mode of operation. In the ON state (first quadrant) of operation of the conventional power MOSFET device 10, current is allowed to flow between the drain contact 32 and the source contacts 30 of the device. As a result of the respective electric fields presented by the deep well regions 20, the current is constricted into a JFET channel. At a certain vertical distance when the electric fields presented by the deep well regions 20 become less pronounced, the current laterally spreads to fill the drift layer 14. Because the external bypass diode 40 is reverse biased, current does not flow from through the device.
FIG. 6B shows operation of the conventional power MOSFET device 10 including the external bypass diode 40 when the conventional power MOSFET device 10 is operating in the third quadrant. When a voltage below the threshold voltage of the conventional power MOSFET device 10 is applied to the gate contact 28 and a positive voltage is applied to the source contacts 30, the conventional power MOSFET device 10 begins to operate in the third quadrant, while the external bypass diode 40 is placed in a forward bias mode of operation. In the forward bias mode of operation of the external bypass diode 40, current (shown by the shaded region in FIG. 6) flows from the anode 42 into the drift layer 46, where it is delivered to the cathode 44 of the external bypass diode 40. Although the external bypass diode 40 creates a low impedance path for current flow between the source contacts 30 and the drain contact 32, a small amount of current may still flow through each one of the deep well regions 20 and into the drift layer 14 of the conventional power MOSFET device 10. This may be due at least in part to the inductance associated with the connections between the external bypass diode 40 and the conventional power MOSFET device 10 and the packaging of the external bypass diode 40.
By creating a high-speed, low-impedance path for current flow around the drift layer 14 of the conventional power MOSFET device 10, the overall current through the drift layer 14 can be substantially reduced. However, even a small amount of current flow in the drift layer 14 while the conventional power MOSFET device 10 is operating in the third quadrant may generate stacking faults over a long enough period of time, thereby significantly degrading the performance of the device. Although the area of the external bypass diode 40 can be increased in an attempt to prevent current flow through the P-N junctions in the conventional power MOSFET device 10 altogether, the area required by the external bypass diode 40 for such a solution is impractical for most applications.
Accordingly, there is a need for a power MOSFET device including a bypass diode that effectively prevents current flow through the drift layer of the power MOSFET device, while minimizing the total area of the device.